A problem VLSI circuit designers face is how to minimize noise in the on chip power supply buses. Many factors contribute to noise in the power supply buses. One such factor, for example, is the switching of high speed output buffer circuitry. As the speed of transition is increased by increasing the drive capability of the output buffer circuits, the parasitic inductance associated with the connection of the output buffer circuits to the power supply buses increases, thereby generating noise. Other contributing factors include chip size and refresh current. Larger chip sizes for increased memory capacity devices have longer on chip power supply buses and therefore have more inductance. In dynamic random access memory devices, DRAM's (as in 16 megabit DRAM's having 2.sup.24 memory cells), higher currents for refresh cycles result in higher voltage drops in the Vss and Vdd buses.
Designers try to minimize noise in the on chip power supply buses in a variety of ways. Improved output buffer circuits switching at different times minimizes "dirty" voltage. Output buffer circuits near power supply bonding pads along the edge of the silicon die reduces the length of current travel. Short wire bonds connecting the power supply bonding pads to lead fingers of the lead frame further reduce inductance.
In 16MB DRAM design, new techniques are required to further minimize noise in the on chip power supply buses.
It it an object, therefore, of this invention is to provide an integrated circuit device whose power supply buses are constructed to minimize noise.
Other objects and advantages of this invention will be apparent to those of ordinary skill in the art having references to the following specification, together with the drawings.